1. Field of the Invention
The present invention generally relates to hierarchical integrated circuit designs and more particularly to a system and methodology that simplifies the automated modification of the hierarchical design. The invention relates to automated modifications accomplished through the use of optimization which is guided by an objective function, and constrained by a formula-based hierarchical layout. The invention simplifies the formula in the formula-based hierarchical layout by the substitution of constants for selected variables such that only two-variable formulae remain in the simplified formula-based layout, thus enabling the use of practical, efficient optimization methods, specifically avoiding the need to solve general integer programming problems.
2. Description of the Related Art
Conventional systems that utilize integrated circuit design layout optimization techniques have been studied in the literature in several contexts. The traditional symbolic layout to physical layout translation takes the form of compaction followed by wire-length minimization, Y. Z. Liao, C. K. Wong, “An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints”, Proc. of DAC, June, 1983, pp. 107–112; and Sching L. Lin, Jonathan Allen, “Minplex—A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout”, Proc. DAC, June, 1986, pp. 123–130 (incorporated herein by reference). In yield enhancement, some parts of a layout are frozen and wires are spread apart. In design migration, the problem is formulated as a minimum perturbation problem, F. L. Heng, Z. Chen, G. Tellez, “A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation,” in Proc. ISPD, pp. 116–121, 1997 (incorporated herein by reference). In some specific scenarios, such as electromigration reliability enhancement, a special algorithm has been developed to speed up the layout optimization process, Z. Chen, F. L. Heng, “A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement” in Proc. International Symposium on DFT in VLSI Systems, pp. 56–63, November, 1998 (incorporated herein by reference). More recently, “altPSM” compliance layout is legalized in the same layout optimization framework, L. Liebmann and F. Heng, “Optimized phase shift migration,” U.S. Pat. No. 6,083,275, July 2000; and F. Heng, L. Liebmann, and J. Lund, “Application of automated design migration to alternating phase shifted mask design,” in Proc. ISPD, pp. 38–43, April, 2001 (incorporated herein by reference). All the layout optimization techniques aforementioned use a constraint graph, Y. Z. Liao, C. K. Wong, “An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints,” Proc. of DAC, June, 1983, pp. 107–112 (incorporated herein by reference), to capture the design ground rules requirement to ensure the legality of the final layout. The typical layout elements these optimization techniques operate on are shapes in library cells, shapes in small flat macros, and wires residing in one level of layout hierarchy of a large layout. Almost all the optimization scenarios are done in one level of a layout hierarchy where the problem can be solved efficiently using a graph theoretic method. Previous techniques in the hierarchical layout optimization art have focused on the hierarchical compaction problem which solves integer linear programming problems using general purpose software. These approaches, J. F. Lee, D. T. Tang, “HIMALAYAS—A Hierarchical Compaction System with a Minimized Constraint Set,” Proc. ICCAD, 1992, pp. 150–157; and D. Marple, “A hierarchy preserving hierarchical compactor,” Proc. 27th Design Automation Conf., pp. 375–381, 1990. (incorporated herein by reference), suffer from runtime problems with large designs.